This document describes the functionalities of the hardware abstraction layer (HAL) for use in the software stack of quantum computers, as described in CEN/CLC/TR 18202:2025 on "Layer Models for Quantum Computing" [13]. The present document is focused on a high-level functional description of the HAL while additional details on implementation and interfacing are reserved for other future documents.
The word "functional" means within this context that a precise definition of implementation, interfaces, information flows (via instructions, commands, signals, etc.) and values is out of scope. This document concentrates therefore on general descriptions of what the HAL supports and which properties or quantities need to be considered for future specification. It offers mainly an enumeration of characteristics that are considered as relevant as well as a motivation why they are relevant.
The Hardware Abstraction Layer aims to inform higher layers with capabilities and limitations supported by the underlying hardware. It hides many implementation-specific details, and provides a more unified interface to higher layers. This includes instruction translation, resource management, fault tolerant quantum computing, mapping and routing, virtualisation for multi-user environments, and reporting of hardware capabilities.
Not all quantum computers make use of the same paradigm. Annealing quantum computers behave differently from gate-based quantum computers, and therefore their HALs might behave differently as well. The HAL can therefore provide information about the underlying architecture, such as for instance being "gate-based", "annealing" or "simulation". When applicable, the HAL can also select between multiple quantum architectures and even partition a single task into multiple queues to perform calculations in parallel on multiple architectures.
To speed-up progress, the first version of this document puts a focus on gate-based quantum computers, but that does not exclude functional requirements for other architectures. Details of other architectures are left for future revisions of this document.
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