Back

IEC 62530-2:2021

SystemVerilog - Part 2: Universal Verification Methodology Language Reference Manual

General information
Valid from 26.07.2021
Directives or regulations
None
Standard history
Status
Date
Type
Name
26.07.2021
Main
IEC 62530-2:2021(E) establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™. This publication has the status of a double logo IEC/IEEE standard.
*
*
*
PDF
388.88 € incl tax
Standard monitoring