Infoteenus
31 ELEKTROONIKA
Uued standardid
EVS-EN IEC 60749-21:2026
Semiconductor devices - Mechanical and climatic test methods - Part 21: Solderability
Käsitlusala:
This part of IEC 60749 establishes a standard procedure for determining the solderability of device package terminations that are intended to be joined to another surface using tin -lead (SnPb) or lead-free (Pb-free) solder for the attachment.
This test method provides a procedure for ‘dip and look’ solderability testing of through hole, axial and surface mount devices (SMDs) as well as an optional procedure for a board mounting solderability test for SMDs for the purpose of allowing simulation of the soldering process to be used in the device application. The test method also provides optional conditions for ageing.
This test is considered destructive unless otherwise detailed in the relevant specification.
NOTE 1 This test method does not assess the effect of thermal stresses which may occur during the soldering process. Reference should be made IEC 60749-15 or IEC 60749-20.
This test method provides a procedure for ‘dip and look’ solderability testing of through hole, axial and surface mount devices (SMDs) as well as an optional procedure for a board mounting solderability test for SMDs for the purpose of allowing simulation of the soldering process to be used in the device application. The test method also provides optional conditions for ageing.
This test is considered destructive unless otherwise detailed in the relevant specification.
NOTE 1 This test method does not assess the effect of thermal stresses which may occur during the soldering process. Reference should be made IEC 60749-15 or IEC 60749-20.
Alusdokumendid:
EN IEC 60749-21:2026; IEC 60749-21:2025
Asendab:
EVS-EN 60749-21:2011
EVS-EN IEC 61076-2-111:2026
Connectors for electrical and electronic equipment - Product requirements - Part 2-111: Circular connectors - Detail specification for power connectors with m12 screw-locking
Käsitlusala:
This part of IEC 61076-2 describes 4- to 6-way circular connectors with M12 screw-locking with current ratings up to 16A rated current per contact and voltage ratings of 63 V or 630 V, that are typically used for power supply and power applications in industrial premises.
These connectors consist of both, fixed and free connectors either rewirable or non-rewirable. Male connectors have round contacts Ø1,0mm and Ø1,5mm.
The different codings provided by this document prevent the mating of differently coded male or female connectors to any other similarly sized interfaces, covered by other standards and the cross-mating between the different codings provided by this document.
NOTE M12 is the dimension of the thread of the screw locking mechanism of these circular connectors
These connectors consist of both, fixed and free connectors either rewirable or non-rewirable. Male connectors have round contacts Ø1,0mm and Ø1,5mm.
The different codings provided by this document prevent the mating of differently coded male or female connectors to any other similarly sized interfaces, covered by other standards and the cross-mating between the different codings provided by this document.
NOTE M12 is the dimension of the thread of the screw locking mechanism of these circular connectors
Alusdokumendid:
EN IEC 61076-2-111:2026; IEC 61076-2-111:2025
Asendab:
EVS-EN IEC 61076-2-111:2018
EVS-EN IEC 60749-23:2026
Semiconductor devices - Mechanical and climatic test methods - Part 23: High temperature operating life
Käsitlusala:
This test is used to determine the effects of bias conditions and temperature on solid state devices over time. It simulates the device operating condition in an accelerated way, and is primarily for device qualification and reliability monitoring. A form of high temperature bias life using a short duration, popularly known as “burn-in”, may be used to screen for infant mortality related failures. The detailed use and application of burn-in is outside the scope of this standard.
Alusdokumendid:
EN IEC 60749-23:2026; IEC 60749-23:2025
Asendatud standardid
EVS-EN 60749-21:2011
Semiconductor devices - Mechanical and climatic test methods - Part 21: Solderability
Käsitlusala:
This part of IEC 60749 establishes a standard procedure for determining the solderability of device package terminations that are intended to be joined to another surface using tin-lead (SnPb) or lead-free (Pb-free) solder for the attachment. This test method provides a procedure for ‘dip and look’ solderability testing of through hole, axial and surface mount devices (SMDs) as well as an optional procedure for a board mounting solderability test for SMDs for the purpose of allowing simulation of the soldering process to be used in the device application. The test method also provides optional conditions for ageing. This test is considered destructive unless otherwise detailed in the relevant specification.
Alusdokumendid:
IEC 60749-21:2011; EN 60749-21:2011
Asendatud:
EVS-EN IEC 60749-21:2026
EVS-EN 60749-23:2004
Semiconductor devices - Mechanical and climatic test methods - Part 23: High temperature operating life
Käsitlusala:
This test is used to determine the effects of bias conditions and temperature on solid state devices over time. It simulates the device operating condition in an accelerated way, and is primarily used for device qualification and reliability monitoring.
Alusdokumendid:
IEC 60749-23:2004; EN 60749-23:2004
Asendatud:
EVS-EN IEC 60749-23:2026
EVS-EN 60749-23:2004/A1:2011
Semiconductor devices - Mechanical and climatic test methods - Part 23: High temperature operating life
Käsitlusala:
This test is used to determine the effects of bias conditions and temperature on solid state devices over time. It simulates the device operating condition in an accelerated way, and is primarily used for device qualification and reliability monitoring.
Alusdokumendid:
IEC 60749-23:2004/A1:2011; EN 60749-23:2004/A1:2011
Asendatud:
EVS-EN IEC 60749-23:2026
EVS-EN IEC 61076-2-111:2018
Connectors for electrical and electronic equipment - Product requirements - Part 2-111: Circular connectors - Detail specification for power connectors with M12 screw-locking
Käsitlusala:
IEC 61076-2-111:2017 specifies 4 to 6-way circular connectors with M12 screw-locking with current ratings up to 16 A and voltage ratings of 63 V or 630 V, that are typically used for power supply and power applications in industrial premises. These connectors consist of both, fixed and free connectors either rewireable or non-rewireable, with M12 screw-locking. Male connectors have round contacts Ø1,0 mm and Ø1,5 mm.
The different codings provided by this document prevent the mating of accordingly coded male or female connectors to any other similarly sized interfaces, covered by other standards and the cross-mating between the different codings provided by this document.
M12 is the dimension of the thread of the screw locking mechanism of these circular connectors.
The different codings provided by this document prevent the mating of accordingly coded male or female connectors to any other similarly sized interfaces, covered by other standards and the cross-mating between the different codings provided by this document.
M12 is the dimension of the thread of the screw locking mechanism of these circular connectors.
Alusdokumendid:
IEC 61076-2-111:2017; EN IEC 61076-2-111:2018
Asendatud:
EVS-EN IEC 61076-2-111:2026
Kavandid
prEN IEC 60749-29:2026
Semiconductor devices - Mechanical and climatic test methods - Part 29: Latch-up test
Käsitlusala:
The objective and scope of this document is to establish test methods that replicate latch-up failures during device operation while providing reliable, repeatable latch-up test results from tester to tester, notwithstanding of device type. This part of IEC 60749-29 establishes the procedure for testing, evaluation and classification of devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined latch-up stress. The document will also provide guidelines to allow the user to apply engineering judgement when historical testing methods are not compatible with the integrated circuit’s functionality.
This document applies to a current-injection test (Signal Pin Test) and an overvoltage test (Supply Test). Current injection is achieved either by current forcing with voltage compliance limit (I Test) or by applying voltage with current compliance limit (E Test).
This document will only consider direct current injection into and out of a signal pin (formerly called I/O pin), and overvoltage on the power supply pins. Transient induced latch -up will not be addressed. A transient-induced latch-up characterization methodology is defined in the ANSI/ESD Standard Practice SP5.4.1-2017 “Latch-up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits – Transient Latch-up Testing, Device Level”.
Latch-up failures are limited to the detection of a sustained low-impedance path resulting from an applied trigger condition. Other types of potential functional failures, including logic state changes and spurious resets, are not considered by this document, and are not considered latch-up failures.
All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, optoelectronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are evaluated according to this document. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies including some Silicon-On-Insulator (SOI).
Transient induced latch-up is not considered; therefore, this document only considers direct current injection into and out of a signal pin (formerly called I/O pin), and overvoltage on the power supply pins. A transient-induced latch-up characterization methodology is defined in the ANSI/ESD Standard Practice SP5.4.1-2017 “Latch-up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits – Transient Latch-up Testing, Device Level”.
Latch-up failures are limited to the detection of a sustained low-impedance path resulting from an applied trigger condition. Other types of potential functional failures, including logic state changes and spurious resets, are not considered by this document, and are not considered latch-up failures.
This document applies to a current-injection test (Signal Pin Test) and an overvoltage test (Supply Test). Current injection is achieved either by current forcing with voltage compliance limit (I Test) or by applying voltage with current compliance limit (E Test).
This document will only consider direct current injection into and out of a signal pin (formerly called I/O pin), and overvoltage on the power supply pins. Transient induced latch -up will not be addressed. A transient-induced latch-up characterization methodology is defined in the ANSI/ESD Standard Practice SP5.4.1-2017 “Latch-up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits – Transient Latch-up Testing, Device Level”.
Latch-up failures are limited to the detection of a sustained low-impedance path resulting from an applied trigger condition. Other types of potential functional failures, including logic state changes and spurious resets, are not considered by this document, and are not considered latch-up failures.
All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, optoelectronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are evaluated according to this document. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies including some Silicon-On-Insulator (SOI).
Transient induced latch-up is not considered; therefore, this document only considers direct current injection into and out of a signal pin (formerly called I/O pin), and overvoltage on the power supply pins. A transient-induced latch-up characterization methodology is defined in the ANSI/ESD Standard Practice SP5.4.1-2017 “Latch-up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits – Transient Latch-up Testing, Device Level”.
Latch-up failures are limited to the detection of a sustained low-impedance path resulting from an applied trigger condition. Other types of potential functional failures, including logic state changes and spurious resets, are not considered by this document, and are not considered latch-up failures.
Alusdokumendid:
47/2991/CDV; prEN IEC 60749-29:2026